In recent years, high-speed MOSFETs, MODFETs, and HEMTs have been proposed, using as the channel region a strained Si (silicon) layer grown epitaxially on Si substrate with an SiGe (silicon-germanium) layer intervening. In a strained-Si FET, tensile stress arises in the Si layer due to the SiGe, which has larger lattice constants than does Si, and consequently the band structure in the Si changes, state degeneration is removed, and carrier mobilities are increased. Hence by using such a strained Si layer as a channel region, operation can be made faster by a factor of 1.3 to 8 compared with normal devices. Moreover, normal Si substrate grown using the CZ method can be employed as the substrate, so that conventional CMOS processes can be employed to realize high-speed CMOS devices.
However, in order to achieve epitaxial growth of the desired strained Si layer described above as the channel region of a FET, a good-quality SiGe layer must be grown epitaxially on the Si substrate; but differences in the lattice constants of Si and SiGe have resulted in crystallinity-related problems such as dislocations. Consequently in the past there have been various proposals such as the following.
Methods which have been proposed include, for example, a method of using a buffer layer in which the Ge (germanium) composition ratio of the SiGe is changed with a constant gradual gradient; a method of using a buffer layer in which the Ge composition ratio is changed in steps (step-shape); a method of using a buffer layer in which the Ge composition ratio is changed in the manner of a superlattice; and a method in which a Si off-cut wafer is used, and a buffer layer is used in which the Ge composition ratio is changed with a constant gradient.                Patent References are as follows.        Patent Reference 1: U.S. Pat. No. 6,107,653        Patent Reference 2: U.S. Pat. No. 5,442,205        Patent Reference 3: U.S. Pat. No. 5,221,413        Patent Reference 4: International Patent No. 98/00857        Patent Reference 5: Japanese Unexamined Patent Application, First Publication No. 6-252046        
However, the following problems remain in the above-described technology of the prior art.
That is, the penetrating dislocation density and surface roughness of a SiGe layer deposited using the above-described conventional art does not attain the level desired for use in devices and manufacturing processes.
For example, when using a buffer layer in which the Ge composition ratio has a gradient, the penetrating dislocation density can be made comparatively low, but there is the problem that the surface roughness worsens; conversely, when using a buffer layer in which the Ge composition ratio is changed in a step-like fashion, the surface roughness can be made comparatively small, but there is the problem that the penetrating dislocation density increases. Further, when an off-cut wafer is used, dislocations tend to emerge laterally rather than in the film thickness direction, but a sufficiently low dislocation density is not achieved. And with respect to surface roughness also, the level required by photolithography processes in the manufacture of LSI and other devices in recent years has not been attained.